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An asynchronous hierarchical router for networks-on-chip-based three-dimensional multi-processor system-on-chip.
Walid Lafi
Didier Lattard
Ahmed Amine Jerraya
Published in:
Softw. Pract. Exp. (2012)
Keyphrases
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multi processor
network on chip
three dimensional
program execution
single processor
shared memory
routing algorithm
multi core processors
interconnection networks
high speed
low cost
parallel architectures
network simulator
orders of magnitude
distributed memory
lower bound
real time