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Efficient Router Architecture for Trace Reduction During NoC Post-Silicon Validation.
Sidhartha Sankar Rout
Suyog Bhimrao Patil
Vaibhav Ishwarlal Chaudhari
Sujay Deb
Published in:
SoCC (2019)
Keyphrases
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network on chip
multi processor
data flow
neural network
software architecture
network simulator