High Performance and Hardware-Efficient Approximate BPF Decoder for Polar codes.
Yuxuan CuiChenggang YanWeiqiang LiuPublished in: ISCAS (2023)
Keyphrases
- error detection
- error control
- reed solomon
- error correction
- decoding algorithm
- low cost
- real time
- joint source channel
- low density parity check
- scientific computing
- hardware and software
- embedded processors
- ldpc codes
- signal processor
- convolutional codes
- fpga implementation
- low latency
- hardware implementation
- variable length
- low complexity
- computer systems
- error concealment
- image processing
- reed solomon codes
- error resilient
- hardware architecture
- signal processing
- coding scheme
- bitstream
- low power
- graphics processing units
- channel coding
- vlsi implementation
- turbo codes
- image transmission
- distributed video coding
- low power consumption
- video codec
- fourier analysis
- computing systems
- rate allocation
- frequency domain
- single chip