A 32kB 2R/1W L1 data cache in 45nm SOI technology for the POWER7TM processor.
Jürgen PilleDieter F. WendelOtto WagnerRolf SautterWolfgang PenthThomas FröhnelStefan BüttnerOtto A. TorreiterMartin EckertJose ParedesDavid HruseckyDavid RayMiles CanadaPublished in: ISSCC (2010)