A scalable parallel hardware architecture for connected component labeling.
Chung-Yuan LinSz-Yan LiTsung-Han TsaiPublished in: ICIP (2010)
Keyphrases
- hardware architecture
- connected component labeling
- processing elements
- hardware implementation
- binary images
- connected components
- hardware architectures
- field programmable gate array
- parallel processing
- associative memory
- morphological operations
- parallel computing
- parallel implementation
- parallel architecture
- massively parallel
- quadtree
- feature selection
- signal processing
- color images
- multiresolution