An improved CMOS ring oscillator PLL with less than 4ps RMS accumulated jitter.

Stephen Williams Hugh Thompson Mike Hufford Eric Naviasky

Published in: CICC (2004)

Keyphrases

high speed
low cost
power consumption
power supply
vlsi circuits
data sets
low power
single chip
root mean square
circuit design
database
genetic algorithm
differential equations
feedback loop
end to end delay
analog vlsi