Enhancing Performance of Gabriel Graph-Based Classifiers by a Hardware Co-Processor for Embedded System Applications.
Janier Arias-GarciaAugusto MafraLiliane GadeFrederico CoelhoCristiano Leite CastroLuiz C. B. TorresAntônio de Pádua BragaPublished in: IEEE Trans. Ind. Informatics (2021)
Keyphrases
- single chip
- semi supervised dimensionality reduction
- high end
- real time
- training data
- computer architecture
- processor core
- support vector
- low cost
- semi supervised
- multi core processors
- ibm zenterprise
- hardware and software
- industry standard
- memory management
- training set
- parallel architectures
- high speed
- feature selection
- decision trees
- computing power
- naive bayes
- embedded processors
- processing elements
- instruction set
- machine learning algorithms
- parallel architecture
- parallel processors
- central processor
- graph model
- hardware implementation
- computer systems
- classification algorithm
- multithreading
- chip design
- machine learning
- error detection
- parallel processing
- text classification
- dimensionality reduction
- computing systems
- power consumption
- memory hierarchy
- svm classifier
- class labels
- feature set
- memory subsystem
- ibm power processor
- general purpose processors
- classification accuracy