Leakage aware SER reduction technique for UDSM logic circuits.

Praveen Elakkumanan Vishwanath Ananthakrishnan Ashok Narasimhan Ramalingam Sridhar

Published in: SoCC (2004)

Keyphrases

logic circuits
low power
functional decomposition
tunnel diode
logic synthesis
high speed
gate array
low cost
sensor networks
computational intelligence
parallel processing