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Leakage aware SER reduction technique for UDSM logic circuits.

Praveen ElakkumananVishwanath AnanthakrishnanAshok NarasimhanRamalingam Sridhar
Published in: SoCC (2004)
Keyphrases
  • logic circuits
  • low power
  • functional decomposition
  • tunnel diode
  • logic synthesis
  • high speed
  • gate array
  • low cost
  • sensor networks
  • computational intelligence
  • parallel processing