Hardware implementation of BLTL property checkers for acceleration of statistical model checking.
Kosuke OshimaTakeshi MatsumotoMasahiro FujitaPublished in: ICCAD (2013)
Keyphrases
- model checking
- hardware implementation
- temporal logic
- efficient implementation
- signal processing
- automated verification
- model checker
- formal specification
- formal verification
- temporal properties
- finite state
- software implementation
- verification method
- reachability analysis
- finite state machines
- computation tree logic
- field programmable gate array
- image processing algorithms
- symbolic model checking
- pspace complete
- partial order reduction
- epistemic logic
- bounded model checking
- process algebra
- transition systems
- neural network
- deterministic finite automaton
- timed automata
- formal methods
- general purpose
- concurrent systems
- satisfiability problem
- description language
- fpga device
- modal logic
- reactive systems
- object oriented
- alternating time temporal logic
- asynchronous circuits