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A Scalable VLSI Architecture for Binary Prefix Sums.

Rong LinKoji NakanoStephan OlariuMaria Cristina PinottiJames L. SchwingAlbert Y. Zomaya
Published in: IPPS/SPDP (1998)
Keyphrases
  • vlsi architecture
  • low complexity
  • vlsi implementation
  • low power
  • real time
  • binary matrix
  • data structure
  • low cost
  • power consumption
  • non binary
  • high speed
  • multiscale