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A Scalable VLSI Architecture for Binary Prefix Sums.
Rong Lin
Koji Nakano
Stephan Olariu
Maria Cristina Pinotti
James L. Schwing
Albert Y. Zomaya
Published in:
IPPS/SPDP (1998)
Keyphrases
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vlsi architecture
low complexity
vlsi implementation
low power
real time
binary matrix
data structure
low cost
power consumption
non binary
high speed
multiscale