Dynamic Power Reduction in a Novel CMOS 5T-SRAM for Low-Power SoC.

Hooman Jarollahi Richard F. Hobson

Published in: CDES (2010)

Keyphrases

low power
power reduction
power consumption
high speed
low cost
single chip
power saving
cmos technology
digital signal processing
low power consumption
vlsi circuits
power dissipation
logic circuits
energy efficiency
image sensor
mixed signal
data flow
parallel processing
data center
computer simulation