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Shift register multi-phase clock based downsampled floating tap DFE for serial links.
Pervez M. Aziz
Hiroshi Kimura
Amaresh V. Malipatil
Shiva Kotagiri
Gordon Chan
Hairong Gao
Published in:
ISCAS (2014)
Keyphrases
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shift register
high speed
random number generator
hardware implementation
social networks
software development
power consumption
link analysis
training phase
learning phase
decision feedback