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Shift register multi-phase clock based downsampled floating tap DFE for serial links.

Pervez M. AzizHiroshi KimuraAmaresh V. MalipatilShiva KotagiriGordon ChanHairong Gao
Published in: ISCAS (2014)
Keyphrases
  • shift register
  • high speed
  • random number generator
  • hardware implementation
  • social networks
  • software development
  • power consumption
  • link analysis
  • training phase
  • learning phase
  • decision feedback