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A 1.2v 11b 100Msps 15mW ADC realized using 2.5b pipelined stage followed by time interleaved SAR in 65nm digital CMOS process.
Pratap Narayan Singh
Ashish Kumar
Chandrajit Debnath
Rakesh Malik
Published in:
CICC (2008)
Keyphrases
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power consumption
synthetic aperture radar
sigma delta
parameter estimation
synthetic aperture radar images
analog to digital converter
image reconstruction
spatial domain
sar images
digital media
digital curves
digital technologies
automatic target recognition