A low-power VLSI architecture for turbo decoding.

Seok-Jun Lee Naresh R. Shanbhag Andrew C. Singer

Published in: ISLPED (2003)

Keyphrases

vlsi architecture
low power
turbo codes
low cost
power consumption
high speed
low density parity check
decoding algorithm
error correction
channel coding
real time
compressed images
low power consumption
ldpc codes