A Hardware Architecture of CABAC Encoding and Decoding with Dynamic Pipeline for H.264/AVC.
Lingfeng LiYang SongShen LiTakeshi IkenagaSatoshi GotoPublished in: J. Signal Process. Syst. (2008)
Keyphrases
- hardware architecture
- decoding process
- coding efficiency
- video coding
- error resilience
- hardware implementation
- bit rate
- image coding
- hardware architectures
- mode decision
- bitstream
- inter frame
- inter layer
- image sequences
- mode selection
- mpeg avc
- video decoder
- video codec
- low complexity
- rate distortion
- motion estimation
- video coding standard
- macroblock
- video encoder
- wavelet transform
- computational complexity
- pattern recognition
- real time