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A 1-60 GHz 9.6 mW 0.18 V Output-Swing Static Clock Divider Circuit in 45-nm SOI CMOS.
Sami Ur Rehman
Ali Ferchichi
Mohammad Mahdi Khafaji
Corrado Carta
Frank Ellinger
Published in:
ICECS (2018)
Keyphrases
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high end
power consumption
clock gating
silicon on insulator
cmos technology
low power
clock frequency
power dissipation
nm technology
power reduction
high speed
power management
duty cycle
low voltage
feedback loop
delay insensitive
neural network
vlsi circuits
metal oxide semiconductor