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A Low-Power and Area-Efficient Design of a Weighted Pseudorandom Test-Pattern Generator for a Test-Per-Scan Built-in Self-Test Architecture.
Vishnupriya Shivakumar
Chinnaiyan Senthilpari
Zubaida Yusoff
Published in:
IEEE Access (2021)
Keyphrases
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low power
pattern generator
built in self test
vlsi architecture
single chip
power consumption
high speed
low cost
cmos technology
logic circuits
low complexity
digital signal processing
design process
design methodology
design considerations
pseudorandom
random number
mixed signal
vlsi circuits