A clocking technique for FPGA pipelined designs.
Oswaldo CadenasGraham M. MegsonPublished in: J. Syst. Archit. (2004)
Keyphrases
- parallel architecture
- high speed
- hardware implementation
- field programmable gate array
- real time image processing
- real time
- systolic array
- dedicated hardware
- low cost
- signal processing
- circuit design
- verilog hdl
- fpga implementation
- hardware architecture
- design space
- data flow
- single chip
- design principles
- information systems
- power reduction
- digital signal
- genetic algorithm
- databases