A 0.5 V 2.5 μW/MHz Microcontroller with Analog-Assisted Adaptive Body Bias PVT Compensation with 3.13nW/kB SRAM Retention in 55nm Deeply-Depleted Channel CMOS.
Marc PonsChristoph Thomas MüllerDavid RuffieuxJean-Luc NagelStéphane EmeryAndreas BurgShuuji TanahashiYoshitaka TanakaAtsushi TakeuchiPublished in: CICC (2019)
Keyphrases
- cmos technology
- low power
- mixed signal
- nm technology
- power consumption
- low cost
- high speed
- low voltage
- floating gate
- analog vlsi
- vlsi architecture
- parallel processing
- single chip
- image sensor
- cmos image sensor
- random access memory
- long term
- multi channel
- power dissipation
- silicon on insulator
- knowledge base
- power reduction
- circuit design
- control system
- data acquisition
- human body
- delay insensitive
- power management
- data transmission
- embedded dram