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Formal verification of analog circuits in the presence of noise and process variation.
Rajeev Narayanan
Behzad Akbarpour
Mohamed H. Zaki
Sofiène Tahar
Lawrence C. Paulson
Published in:
DATE (2010)
Keyphrases
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formal verification
analog circuits
model checking
real time
genetic algorithm
image processing
xml documents
knowledge representation
high speed
constraint satisfaction problems
fault diagnosis
model checker
symbolic model checking