A DLL based 10-320 MHz clock synchronizer.

Sung-Sik Hwang Ki-Mo Joo Ho-Jin Park Jae-Whui Kim Philip Chung

Published in: ISCAS (2000)

Keyphrases

search algorithm
high speed
max sat
fpga device
clock frequency
power consumption
branch and bound
low power
duty cycle
genetic algorithm
optimal solution
databases
satisfiability problem
hardware implementation
branch and bound algorithm
propositional satisfiability
cmos technology
high frequency