Login / Signup

A 500 MS/s 6 bits delay line ADC with inherit sample & hold.

Ali H. HassanMaged AliNabil MohammedAhmed AliMohammed HassoubhM. Wagih IsmailMohammed RefkyHassan Mostafa
Published in: ICM (2014)
Keyphrases
  • sample size
  • real time
  • error correcting codes
  • databases
  • neural network
  • error correction