A 5-GHz fractional-N phase-locked loop with spur reduction technique in 0.13-μm CMOS.

Wei-Hao Chiu Chien-Yuan Cheng Tsung-Hsien Lin

Published in: ISCAS (2010)

Keyphrases

phase locked loop
high speed
power consumption
low power
analog vlsi
low cost
high voltage
neural network
power supply
rough sets
dual band