FPGA architecture of multi-codeword LDPC decoder with efficient BRAM utilization.

Sergiu Nimara Oana Boncalo Alexandru Amaricai Mircea Popa

Published in: DDECS (2016)

Keyphrases

fpga implementation
real time
hardware implementation
hardware architecture
hardware design
parallel architecture
low density parity check
hardware architectures
software implementation
error concealment
vector quantization
high speed
low cost
low complexity
turbo codes
dedicated hardware
ldpc codes