A 0.076 mm2 12 b 26.5 mW 600 MS/s 4-Way Interleaved Subranging SAR-ΔΣ ADC With On-Chip Buffer in 28 nm CMOS.
Alessandro VencaNicola GhittoriAlessandro BosiClaudio NaniPublished in: IEEE J. Solid State Circuits (2016)
Keyphrases
- power consumption
- clock frequency
- nm technology
- cmos technology
- low power
- power dissipation
- synthetic aperture radar
- silicon on insulator
- single chip
- power management
- sar images
- low voltage
- analog to digital converter
- wide dynamic range
- mixed signal
- low power consumption
- rms error
- buffer size
- image sensor
- cmos image sensor
- image reconstruction
- power supply
- digital signal processing
- parallel processing
- high speed
- electro optic
- infrared
- parameter estimation