Useful-Skew Clock Routing with Gate Sizing for Low Power Design.
Joe G. XiWayne Wei-Ming DaiPublished in: J. VLSI Signal Process. (1997)
Keyphrases
- low power
- power consumption
- cmos technology
- high speed
- single chip
- low power consumption
- nm technology
- low cost
- vlsi architecture
- logic circuits
- digital signal processing
- power dissipation
- gate array
- wireless transmission
- design process
- high power
- mixed signal
- vlsi circuits
- image sensor
- parallel processing
- ultra low power
- power saving
- low voltage
- power reduction