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Transistor-level estimation of worst-case delays in MOS VLSI circuits.
Michel Dagenais
Serge Gaiotti
Nicholas C. Rumin
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (1992)
Keyphrases
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vlsi circuits
worst case
low power
lower bound
integrated circuit
high speed
error bounds
upper bound
low cost
dynamic systems
average case
pattern matching
machine vision
mixed signal