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Transistor-level estimation of worst-case delays in MOS VLSI circuits.

Michel DagenaisSerge GaiottiNicholas C. Rumin
Published in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (1992)
Keyphrases
  • vlsi circuits
  • worst case
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  • high speed
  • error bounds
  • upper bound
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  • dynamic systems
  • average case
  • pattern matching
  • machine vision
  • mixed signal