Login / Signup
A 10T SRAM architecture with 40 % enhanced throughput for IMC applications benchmarked with CIFAR-10 dataset.
Ravi S. Siddanath
Mohit Gupta
Chaitanya Joshi
Manish Goswami
Kavindra Kandpal
Published in:
Integr. (2024)
Keyphrases
</>
control architecture
management system
response time
design considerations
real time
software architecture
power consumption
network architecture
database
training dataset
process control
middle layer
benchmark datasets