A 2.5-ns clock access, 250-MHz, 256-Mb SDRAM with synchronous mirror delay.
Takanori SaekiYuji NakaokaMamoru FujitaAkihito TanakaKyoichi NagataKenichi SakakibaraTatsuya MatanoYukio HoshinoKazutaka MiyanoSatoshi IsaShigeyuki NakazawaEiichiro KakehashiJohn Mark DrynanMasahiro KomuroTadashi FukaseHaruo IwasakiMotohiro TakenakaJunichi SekineMasahiko IgetaNobuko NakanishiToshiro ItaniKazuyoshi YoshidaHiroshi YoshinoSyuichi HashimotoTsuyoshi YoshiiMichihiko ichinoseTomoo imuraMasato UziieShinichi KikuchiKuniaki KoyamaYukio FukuzoTakashi OkudaPublished in: IEEE J. Solid State Circuits (1996)