A 1 V Phase Locked Loop with Leakage Compensation in 0.13 µm CMOS Technology.

Chi-Nan Chuang Shen-Iuan Liu

Published in: IEICE Trans. Electron. (2006)

Keyphrases

cmos technology
phase locked loop
low power
spl times
low voltage
power consumption
parallel processing
power dissipation
multipath
high speed
low cost
high voltage
mixed signal
image sensor
silicon on insulator
image processing
neural network
fuzzy logic
digital images
control system