Power-Efficient LDPC Decoder Architecture Based on Accelerated Message-Passing Schedule.
Kazunori ShimizuTatsuyuki IshikawaNozomu TogawaTakeshi IkenagaSatoshi GotoPublished in: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2006)
Keyphrases
- message passing
- ldpc codes
- low density parity check
- belief propagation
- distributed systems
- shared memory
- factor graphs
- markov random field
- inference in graphical models
- decoding algorithm
- error correction
- multithreading
- graphical models
- sum product algorithm
- distributed shared memory
- channel coding
- sum product
- np hard
- distributed video coding
- graph cuts
- distributed source coding