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CMOS circuit verification with symbolic switch-level timingsimulation.
Clayton B. McDonald
Randal E. Bryant
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2001)
Keyphrases
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high speed
circuit design
analog vlsi
power consumption
delay insensitive
functional verification
higher level
levels of abstraction
low power
high level
power dissipation
vlsi circuits
genetic algorithm
information systems
low cost
cmos technology