A 0.6 V Dual-Rail Compiler SRAM Design on 45 nm CMOS Technology With Adaptive SRAM Power for Lower VDD_min VLSIs.
Yen-Huei ChenGary ChanShao-Yu ChouHsien-Yu PanJui-Jen WuRobin LeeHung-Jen LiaoHiroyuki YamauchiPublished in: IEEE J. Solid State Circuits (2009)
Keyphrases
- cmos technology
- power consumption
- low power
- power dissipation
- spl times
- low voltage
- high speed
- power reduction
- power management
- mixed signal
- parallel processing
- silicon on insulator
- low cost
- energy saving
- image sensor
- digital signal processing
- embedded dram
- image processing
- design methodology
- computer systems
- case study