Improved Redundant Binary Adder Realization in FPGA.

Satya Ranjan Sahu Bandan Kumar Bhoi Manoranjan Pradhan

Published in: J. Circuits Syst. Comput. (2021)

Keyphrases

high speed
hardware implementation
low cost
non binary
evolutionary algorithm
highly redundant
logic circuits
real time image processing
hardware design
signal processing
real time
pattern recognition
multiscale
image processing
artificial intelligence
machine learning
real world
neural network
data sets