Manoranjan Pradhan

Publication Activity (10 Years)

Years Active: 2017-2021
Publications (10 Years): 6

Top Topics

Binary Representation

Top Venues

J. Circuits Syst. Comput.

IET Comput. Digit. Tech.

Comput. Electr. Eng.

IET Circuits Devices Syst.

Publications

Satya Ranjan Sahu, Bandan Kumar Bhoi, Manoranjan Pradhan
Improved Redundant Binary Adder Realization in FPGA. J. Circuits Syst. Comput. 30 (16) (2021)
Satya Ranjan Sahu, Bandan Kumar Bhoi, Manoranjan Pradhan
Fast signed multiplier using Vedic Nikhilam algorithm. IET Circuits Devices Syst. 14 (8) (2020)
Ranjan Kumar Barik, Bandan Kumar Bhoi, Manoranjan Pradhan
An efficient redundant binary adder with revised computational rules. Comput. Electr. Eng. 72 (2018)
Ranjan Kumar Barik, Manoranjan Pradhan
Efficient ASIC and FPGA implementation of cube architecture. IET Comput. Digit. Tech. 11 (1) (2017)
Ranjan Kumar Barik, Manoranjan Pradhan, Rutuparna Panda
Efficient Conversion Technique from Redundant Binary to NonRedundant Binary Representation. J. Circuits Syst. Comput. 26 (9) (2017)
Snigdha Subhadarshinee Tripathy, Ranjan Kumar Barik, Manoranjan Pradhan
An Improved Conversion Circuit for Redundant Binary to Conventional Binary Representation. CICBA (1) (2017)