22.4 A 32Gb/s Digital-Intensive Single-Ended PAM-4 Transceiver for High-Speed Memory Interfaces Featuring a 2-Tap Time-Based Decision Feedback Equalizer and an In-Situ Channel-Loss Monitor.
Po-Wei ChiuChris H. KimPublished in: ISSCC (2020)
Keyphrases
- decision feedback
- high speed
- error propagation
- multipath
- bit error rate
- intersymbol interference
- soft decision
- low power
- real time
- phase locked loop
- wireless channels
- channel coding
- frame rate
- packet loss
- additive white gaussian noise
- gigabit ethernet
- data acquisition
- viterbi algorithm
- orthogonal frequency division multiplexing
- video quality
- coding efficiency
- communication systems
- channel estimation
- computer simulation
- end to end