Power noise in 14, 10, and 7 nm FinFET CMOS technologies.
Ravi PatelEby G. FriedmanPraveen RaghavanPublished in: ISCAS (2016)
Keyphrases
- power consumption
- silicon on insulator
- nm technology
- missing data
- cmos technology
- low cost
- power reduction
- low power
- random noise
- power management
- noise level
- additive noise
- power dissipation
- noise model
- ibm power processor
- circuit design
- noisy data
- high speed
- ultra low power
- emerging technologies
- neural network
- high resolution