A fixed latency ORBGRAND decoder architecture with LUT-aided error-pattern scheduling.
Carlo CondoPublished in: CoRR (2021)
Keyphrases
- heterogeneous computing
- scheduling problem
- lookup table
- associative memory
- error rate
- pattern matching
- scheduling algorithm
- low complexity
- real time
- resource constraints
- error bounds
- data flow
- response time
- resource utilization
- parallel processors
- fpga implementation
- image compression
- error detection
- parallel architecture
- motion estimation
- management system