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A PVT Tolerant 10 to 500 MHz All-Digital Phase-Locked Loop With Coupled TDC and DCO.

Wei LiuWei (Ruth) LiPeng RenChinglong LinShengdong ZhangYangyuan Wang
Published in: IEEE J. Solid State Circuits (2010)
Keyphrases
  • phase locked loop
  • multipath
  • high voltage
  • high speed
  • real time
  • neural network
  • training data
  • wireless sensor networks
  • computer systems
  • digital content
  • circuit design