Low Power Probabilistic Floating Point Multiplier Design.
Aman GuptaSatyam MandavalliVincent John MooneyKeck Voon LingArindam BasuHenry JohanBudianto TandianusPublished in: ISVLSI (2011)
Keyphrases
- floating point
- low power
- low cost
- power consumption
- single chip
- vlsi architecture
- high speed
- low power consumption
- logic circuits
- fixed point
- digital signal processing
- cmos technology
- gate array
- high power
- instruction set
- nm technology
- power reduction
- probabilistic model
- power dissipation
- mixed signal
- wireless transmission
- vlsi circuits
- sparse matrices
- design process
- ultra low power