Dynamic, non-linear cache architecture for power-sensitive mobile processors.
Garo BournoutianAlex OrailogluPublished in: CODES+ISSS (2010)
Keyphrases
- multithreading
- memory subsystem
- parallel computing
- mobile devices
- embedded processors
- parallel algorithm
- memory hierarchy
- computational power
- instruction set
- parallel processing
- pervasive environments
- parallel architecture
- memory access
- parallel computers
- cache misses
- dynamic content
- processing units
- shared memory
- prefetching
- multiprocessor systems
- power consumption
- mobile phone
- query processing