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A low leakage substrate bias-assisted technique for low voltage dual bit-line SRAM.

Sujata PandeySaket KumarVipul BhatnagarRicha SharmaD. Baba bashaPreeti Dhiman
Published in: Comput. Electr. Eng. (2022)
Keyphrases
  • low voltage
  • random access memory
  • leakage current
  • power line
  • design considerations
  • power management
  • low variance
  • real time
  • computer vision
  • cmos technology