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A two-step 5b logarithmic ADC with minimum step-size of 0.1% full-scale for MLC phase-change memory readout.

Ji-Wook KwonDong-Hwan JinHyeon-June KimSun-Il HwangMin-Chul ShinJong-Ho KangSeung-Tak Ryu
Published in: CICC (2014)
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