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Delay optimization of digital CMOS VLSI circuits by transistor reordering.
Bradley S. Carlson
Suh-Juch Lee
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (1995)
Keyphrases
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vlsi circuits
mixed signal
low power
power dissipation
power consumption
high speed
low cost
cmos technology
multi channel
circuit design
optimization algorithm
single chip
optimization problems
image sensor
low voltage
digital signal processing