Multi-Slew-Rate Output Driver and Optimized Impedance-Calibration Circuit for 66nm 3.0Gb/s/pin DRAM Interface.
Dong-Uk LeeShin-Deok KangNak-Kyu ParkHyun-Woo LeeYoung-Kyoung ChoiJung-Woo LeeSeung-Wook KwackHyeong-Ouk LeeWon-Joo YunSang-Hoon ShinKwan-Weon KimYoung-Jung ChoiYe Seok YangPublished in: ISSCC (2008)