An AES crypto chip using a high-speed parallel pipelined architecture.
Seong-Moo YooDeen KotturiW. David PanJohn BlizzardPublished in: Microprocess. Microsystems (2005)
Keyphrases
- high speed
- pipelined architecture
- hardware implementation
- advanced encryption standard
- low power
- real time
- field programmable gate array
- parallel processing
- low power consumption
- low cost
- parallel computing
- security protocols
- shared memory
- digital signature
- cryptographic algorithms
- high density
- encryption algorithms
- computer vision
- neural network