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Circuit to reduce Gate Induced Drain Leakage in CMOS output buffers.
Hari Anand Ravi
Mayank Goel
Prasad Bhilawadi
Published in:
VLSI-SoC (2014)
Keyphrases
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cmos technology
high speed
low power
circuit design
low voltage
analog vlsi
leakage current
multiple input
power consumption
nm technology
delay insensitive
vlsi circuits
real time
parallel processing
input data
significantly reduced
low cost
asynchronous circuits