A 0.47-0.66 pJ/bit, 4.8-8 Gb/s I/O Transceiver in 65 nm CMOS.
Young-Hoon SongRui BaiKangmin HuNoah Hae-Woong YangPatrick Yin ChiangSamuel PalermoPublished in: IEEE J. Solid State Circuits (2013)
Keyphrases
- nm technology
- high speed
- silicon on insulator
- random access memory
- cmos technology
- low power
- ibm power processor
- ultra low power
- power consumption
- input output
- analog to digital converter
- metal oxide semiconductor
- low cost
- virtual memory
- main memory
- low voltage
- analog vlsi
- power dissipation
- image sensor
- design considerations
- parallel processing
- flip flops
- power management
- error resilience
- power supply
- phase locked loop