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Measuring the effectiveness of symmetric and asymmetric transistor sizing for Single Event Transient mitigation in CMOS 90nm technologies.
Thiago Assis
Fernanda Lima Kastensmidt
Gilson I. Wirth
Ricardo Reis
Published in:
LATW (2009)
Keyphrases
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high speed
low power
metal oxide semiconductor
integrated circuit
low cost
circuit design
neural network
cmos technology
bayesian decision problems
data mining
image sequences
power consumption
st century
silicon on insulator