FPGA Blokus Duo Solver using a massively parallel architecture.
Takashi YozaRetsu MoriwakiYuki TorigaiYuki KamikuboTakayuki KubotaTakahiro WatanabeTakumi FujimoriHiroyuki ItoMasato SeoKouta AkagiYuichiro YamajiMinoru WatanabePublished in: FPT (2013)
Keyphrases
- hardware implementation
- real time image processing
- hardware design
- high speed
- field programmable gate array
- low cost
- signal processing
- real time
- dedicated hardware
- hardware architecture
- software implementation
- digital signal
- quantified boolean formulas
- general purpose
- hardware architectures
- fpga hardware
- verilog hdl
- fpga implementation
- tree search
- orders of magnitude
- pattern recognition
- website
- learning algorithm